Gateways and protocols

A gateway is what turns a component's port into traffic on the fabric. Its name says the component kind on the left and the protocol on the right: c++2DtCan is a CAN port on a C++ component, python2DtEthernet an Ethernet port on a Python component, fmu2DtCan a CAN port on an FMU. Every gateway family below is the vendor's list (Builder and Simulator Guide 2-15 onward); the two rightmost columns are what this workspace has exercised.

component kind	gateways (VENDOR)	exercised here
C++	c++2DtEthernet, c++2DtCan, c++2DtGpio, c++2DtLin, c++2DtPwm, c++2DtSpi, c++2DtGenericPayload	Ethernet, Can, GenericPayload, 63-component twins
Python	python2DtEthernet, python2DtCan, python2DtLin, python2DtGenericPayload, python2DtGpio	Can, GenericPayload in a mixed twin; Ethernet generates invalid Python when the socket carries no signals
SystemC	c++ style gateways on a SystemC client	a 2-component template built and ran (peer session)
FMU	fmu2DtEthernet, fmu2DtCan, fmu2DtGpio, fmu2DtLin, fmu2DtPwm, fmu2DtSpi, fmu2DtGenericPayload	the Amesim QX-250 FMU accepted and run in a 2-component template (peer session)
ROS	ros2DtEthernet, ros2DtCan, ros2DtLin, ros2DtPwm, ros2DtSpi, ros2DtGenericPayload	not tried
Simulink	simulink2DtEthernet, simulink2DtCan, simulink2DtPwm, simulink2DtSpi, simulink2DtGenericPayload	not tried
Virtual platform, vSensor, VEOS, HIL, FMI master	vp*, vSensor*, veos*, fmiMaster* families through VSI Route	not tried; VSI Route is not part of any twin here
RTL	rtlCan2DtCan, rtlAxi2DtAxi, rtlEthernet2DtEthernet, rtlLin2DtLin, rtlMem2DtGenericPayload	not tried; needs Veloce or VPS
Physical	physicalCan2DtCan, physicalEthernet2DtEthernet, physicalUart2DtUart	not tried
CANoe	canoe2DtCan, canoe2DtEthernet, canoe2DtLin	not tried

Protocol behaviour that shapes a twin (EXERCISED unless marked)

• GenericPayload: point to point, the signals declared on the port travel as a packed struct; a source may feed many destinations through separate connect signals lines. The workhorse for anything Teamcenter calls a discrete, a serial link or a control word.
• CAN: a frame id shared by every node that defines it; every node transmits every step; 8 bits per signal in the generated layout; 64 bits per frame; several frame ids per port are allowed. Python CAN ports take -canVersion can or canFd.
• Ethernet: TCP or UDP sockets between exactly two ports; one port carries many sockets; hub-and-spoke for a bus with more than two members; server and client of one number cannot sit on one port. No signals cross the sockets in the Teamcenter-built twins.
• UART: no C++ to C++ gateway exists; folded onto GenericPayload.
• GPIO: c++2DtGpio exists but its signals connect only to a virtual platform; folded onto GenericPayload between generated components.
• SPI and LIN: master and slave roles per port; the generator picks the first port on a bus as master and reports it. Not exercised end to end here.
• AXI and PWM: connect ports; the AXI interface on the Teamcenter tier has no ports, so nothing was generated for it.

How interface classes become protocols in the Teamcenter pipeline

Teamcenter records an interface's class (databus, electrical-signal, optical and so on) but no protocol. gateway_map.json holds the declared mapping from interface name patterns to VSI protocols and is meant to be read and argued with; icd_to_vsi.py prefers an explicit Seg0Implements on the port, falls back to the name rules with a warning, and lists what stays unresolved instead of dropping it. The vsi_protocols list in that file is exactly the set the generator will emit; anything else is refused before a run.

Limits worth checking in the vendor text

The binary's help is the oracle for syntax (see command-grammar). For per-protocol semantics, the Builder and Simulator Guide's chapter 2 gives one section per protocol and one per component kind, and chapter 5 gives the C++ API of each gateway class (VsiCanGateway, VsiEthernetGateway, VsiGenericPayloadGateway and the rest). The page map is in vendor-manuals-map.